The present disclosure relates to a stacked conductor structure such as those that may be used for multi-layer capacitors, power and/or ground plane distribution or electro-magnetic shielding structures.
Modern integrated circuit manufacturing techniques vary in complexity and cost. Typical fabrication techniques for integrated circuit systems, for example, require conductors that interconnect circuit elements to be manufactured according to photolithography techniques involving a complicated series of masks and etchants. After a photoresist material is deposited on a given substrate, a mask is overlaid upon the photoresist. Portions of the material will be exposed to incident radiation and others will not, depending on patterns imposed by the mask. A series of chemical treatments may be applied to the photoresist, which will engrave the mask pattern onto the material.
The process of applying photoresist, radiation exposure and chemical treatment may be repeated multiple times during fabrication of an integrated circuit. The cost of fabrication typically increases with its complexity. Moreover, individual photolithography techniques typically develop two-dimensional structures; if a three-dimensional structure is required (for example, to route one conductor from the bottom of a multi-layer structure to the top), the cost and complexity of fabrication increases because the masks of circuit structures in one layer must be precisely registered with the mask of circuit structures in adjacent layers to build electrical structures that cross between layers. In modern CMOS fabrication techniques, it can be common for a single semiconductor wafer to undergo 20 photolithography cycles or more.
Construction of interconnections for multiple conductor layers in a typical CMOS process usually is done in a sequential basis. For example, to make a connection through four metal layers in a CMOS circuit, multiple via processes would be needed: A first via would be constructed to extend from the first metal layer to the second metal layer. A second via would be constructed to extend from the second metal layer to the third metal layer. A third via would be constructed to extend from the third metal layer to the fourth metal layer. Manufacture of selective interconnect among overlapping metal layers would be even more difficult, as an interconnect that connects the first metal layer only to the fourth metal layer would have to avoid electrical contact with intervening second and third metal layers. Thus, a via that connects layers one and four would have to be insulated from making contact with layers two and three. Such complexities increase the cost of manufacture for such electrical distribution structures in integrated circuits.
Other manufacturing techniques have been proposed to develop structures that traverse vertically across a structure having multiple horizontal layers. It is possible, for example, to drill vias into a multi-layer stack using a mechanical drill and to fill the resultant hole with a conductor material. Such techniques, however, can be error prone and can lead to inadvertent damage of a semiconductor wafer. Moreover, such techniques require the use of expensive machinery—a first machine to fabricate the multi-layer structure that is desired and a second machine to drill the via. Thus, such techniques involve relatively large capital investment.
The inventor perceives a need for development of vertical components in a multi-layer structure with reduced expense. The inventor also perceives a need to provide manufacturing techniques that provide simple, cost-effective connections selectively to metal layers that have substantial overlap regions.